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2. Functional Description
The AT25F1024A is designed to interface directly with the synchronous serial peripheral inter-
face (SPI) of the 6800 type series of microcontrollers.
The AT25F1024A utilizes an 8-bit instruction register. The list of instructions and their operation
codes are contained in Table 2-1 . All instructions, addresses, and data are transferred with the
MSB first and start with a high-to-low transition.
Write is defined as program and/or erase in this specification. The following commands, Pro-
gram, Sector Erase, Chip Erase, and WRSR are write instructions for AT25F1024A.
Table 2-1.
Instruction Set for the AT25F1024A
Instruction
Instruction Name
WREN
WRDI
RDSR
WRSR
READ
PROGRAM
SECTOR ERASE
CHIP ERASE
RDID
Format
0000 X110
0000 X100
0000 X101
0000 X001
0000 X011
0000 X010
0101 X010
0110 X010
0001 X101
Operation
Set Write Enable Latch
Reset Write Enable Latch
Read Status Register
Write Status Register
Read Data from Memory Array
Program Data into Memory Array
Erase One Sector in Memory Array
Erase All Sectors in Memory Array
Read Manufacturer and Product ID
WRITE ENABLE (WREN): The device will power up in the write disable state when V CC is
applied. All write instructions must therefore be preceded by the WREN instruction.
WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the WRDI instruc-
tion disables all write commands. The WRDI instruction is independent of the status of the WP
pin.
READ STATUS REGISTER (RDSR): The RDSR instruction provides access to the status regis-
ter. The Ready/Busy and write enable status of the device can be determined by the RDSR
instruction. Similarly, the Block Write Protection bits indicate the extent of protection employed.
These bits are set by using the WRSR instruction. During internal write cycles, all other com-
mands will be ignored except the RDSR instruction.
Table 2-2.
Status Register Format
Bit 7
WPEN
Bit 6
X
Bit 5
X
Bit 4
X
Bit 3
BP1
Bit 2
BP0
Bit 1
WEN
Bit 0
RDY
8
AT25F1024A
3346G–SFLSH–7/07
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